The present disclosure relates generally to solid state imaging devices used in digital still cameras and the like and methods for manufacturing the same.
MOS (Metal Oxide Semiconductor) solid state imaging devices, including a MOS transistor for amplifying a signal detected by a photodiode in each pixel, have higher sensitivity as compared with CCD (Charge Coupled Device)-type solid state imaging devices.
FIG. 8 is a sectional view schematically illustrating the structure of a unit pixel and an amplifying transistor of a conventional MOS solid state imaging device. In FIG. 8, a photodiode and a transfer transistor are shown as the unit pixel. The structure of the amplifying transfer shown in FIG. 8 is a typical structure of transistors (reset transistors, column selecting transistors, and other transistors: they are all N-type MOS transistors) formed on a semiconductor substrate other than the transfer transistors.
As shown in FIG. 8, a unit pixel 150 and an amplifier transistor 170 are formed in regions defined by isolation regions 102 in a surface portion of a semiconductor substrate 100 where a P-type well region 101(a P-well 101) is formed.
A photodiode 110 constituting the unit pixel 150 includes a P-type impurity region 112 and an N-type impurity region 111 formed in this order from the surface of the substrate. A transfer transistor 120 constituting the unit pixel 150 includes the N-type impurity region 111 of the photodiode 110 as a source region, a floating diffusion layer 160 as a drain region, and a gate electrode 123 formed on the P-well 101 between the N-type impurity region 111 and the floating diffusion layer 160. The floating diffusion layer 160 is formed of a low concentration impurity region 121 adjacent to the gate electrode 123 of the transfer transistor 120 and a high concentration impurity region 122 electrically connected to the low concentration impurity region 121.
The amplifying transistor 170 has a gate electrode 173 formed on the P-well 101, and low concentration impurity regions 171 adjacent to the gate electrode 173 and high concentration impurity regions 172 electrically connected to the low concentration impurity regions 171 as source/drain regions formed in a surface portion of the P-well 101 on both sides of the gate electrode 173.
In order to reduce parasitic resistance of contacts with the source/drain regions, metal silicide layers 124 and 174 are formed on the high concentration impurity region 122 of the floating diffusion layer 160 and the high concentration impurity diffusion regions 172 of the amplifying transistor 170, respectively.
In the conventional unit pixel 150 shown in FIG. 8, signal charges (electrons) generated by photoelectric conversion by the photodiode 110 and accumulated at a PN junction are transferred to the floating diffusion layer 160 when the transfer transistor 120 is brought into conduction. As the floating diffusion layer 160 is connected to the gate electrode 173 of the amplifying transistor 170, a potential of the floating diffusion layer 160 is read through the amplifying transistor 170 to output a pixel signal.
[Patent Document 1] Published Japanese Patent Application No. H7-122733